DRAM Access Steps

The Request Path

When a processor needs data from main memory, the request does not travel directly to an arbitrary stored bit. Main memory is provided by an off-chip DRAM system, so a memory controller coordinates the interface between the processor chip and the DRAM chips. The controller turns changing read and write requests into memory commands while respecting the timing and resource limits imposed by the DRAM hardware.

The controller is therefore a coordination layer, not merely a wire between the processor and memory. It determines which DRAM operation can occur next and arranges the steps needed to make the requested row and column accessible.

Inside a DRAM Array

A DRAM system contains multiple DRAM chips. Each chip contains rectangular storage-cell arrays organized into rows and columns. Each cell stores one bit as charge on a capacitor. Because that charge decreases over time, each cell must be refreshed every few milliseconds so that its stored content is not lost. This periodic refreshing is why the memory is called dynamic RAM.

The row buffer is the key working location in this structure. It temporarily holds the bits from one selected row. A read or write does not treat every cell as an independently open destination; instead, a row is made available in the row buffer, and a column operation selects the requested word from that open row or writes into it.

The Three Access Stages

Suppose a request targets a row that is not currently open. The controller cannot begin with the read or write command for the requested word. It must first make the requested row available in the row buffer. After the read or write, the row-buffer contents must be restored to the array before another row can be opened.

Row Locality

After a row has been activated, it remains the currently open row in the row buffer. A later request to another column in that same row can proceed with a read or write command. It does not require the extra work of precharging the current row and activating a different row.

This performance advantage is called row locality. Row locality is not a separate storage structure. It is an effect created by the row buffer and by the rule that a different row requires precharge followed by activate. The currently open row can therefore serve several column requests without repeating the row-change work.

Managing Pending Requests

The controller does not necessarily handle every processor request in isolation. It maintains a memory transaction queue containing memory-access requests from processors that share the memory system. The queue gives the controller a set of pending work from which it can issue commands to DRAM.

The scheduling problem has two sides. Request patterns change dynamically, but every command must also obey the timing and resource constraints required by the DRAM hardware. With multiple processor cores sharing DRAM, the pending set can become especially difficult to manage. The controller must choose commands that are both useful for pending requests and currently permitted by the memory state and hardware constraints.

Common Reasoning Errors

• Treating a DRAM cell as an independently open location.

  The row must be activated and made available in the row buffer before its words can be read or written.

  Fix: Identify the requested row first, then determine whether it is already open.

• Putting read or write before activate for a closed row.

  A request targeting a row that is not currently open must first make that row available in the row buffer.

  Fix: For a closed-row request, reason through activate, read or write, and then precharge when preparing to change rows.

• Forgetting precharge when switching rows.

  Precharge is required before a different row can be activated.

  Fix: Insert precharge between the operation on the current row and activation of a different row.

• Calling row locality a separate memory structure.

  Row locality is a performance effect created by reusing the currently open row.

  Fix: Explain that same-row accesses avoid the extra precharge and activate work needed for a different row.

• Assuming every queued request can execute immediately.

  The controller must issue commands under timing and resource constraints.

  Fix: Treat the transaction queue as pending work, then check which operation is legal next.

Trace the Next Command

What to Remember

1. The memory controller coordinates requests between the processor and off-chip DRAM.
2. DRAM cells store bits as charge on capacitors inside row-and-column arrays, while the row buffer temporarily holds one selected row.
3. A closed-row access requires activate before read or write, and precharge before a different row can be activated.
4. Row locality lets later requests to the currently open row avoid the extra precharge and activate work required for a different row.
5. A transaction queue gives the controller pending requests to manage while timing and resource constraints determine which command is legal next.